The present invention relates generally to logic circuits and, more particularly, to full-rail differential logic circuits.
One example of a prior art full-rail differential logic circuit is presented and discussed at page 112, and shown in FIG. 3 (c), in xe2x80x9cHIGH SPEED CMOS DESIGN STYLESxe2x80x9d by Bernstein et al. of IBM Microelectronics; Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Mass., 02061; ISBN 0-7923-8220-X, hereinafter referred to as the Bernstein et al. reference, which is incorporated herein by reference, in its entirety, for all purposes.
FIG. 1 shows a prior art full-rail differential logic circuit 100 similar to that discussed in the Bernstein et al. reference. As seen in FIG. 1, prior art full-rail differential logic circuit 100 included six transistors: PFET 105, PFET 107, NFET 109, PFET 115, PFET 117 and NFET 121. Prior art full-rail differential logic circuit 100 also included: differential logic 123 with inputs 151 and 153; out terminal 111; and outBar terminal 113. Prior art full-rail differential logic circuit 100 was activated from a clock signal CLKA. As shown in FIG. 1, signal CLKA was supplied to: gate 116 of PFET 115; gate 118 of PFET 117; gate 129 of NFET 109; and gate 122 of NFET 121.
Prior art full-rail differential logic circuit 100 worked reasonably well under conditions of a light load, for instance under conditions where fan out is less than four. However, prior art full-rail differential logic circuit 100 was less useful under conditions of a heavy load, for instance, in cases where fan out exceeded four. The shortcomings of prior art full-rail differential logic circuit 100 arose primarily because under heavy load conditions logic network 123 had to be increased in size to act as a driver for the next stage in the cascade. This in turn meant that logic network 123 was large, slow and inefficient. The problem was further aggravated as additional prior art full-rail differential logic circuits 100 were cascaded together to form the chains commonly used in the industry. Consequently, the full potential of prior art full-rail differential logic circuits 100 was not realized and their use was narrowly limited to light load applications.
In addition during the evaluation phase, prior art full-rail differential logic circuit 100 drew excess power unnecessarily as the relevant inputs, 151 or 153, to logic network 123 were transitioning low to shut off the path of one of the complementary output terminals, out terminal 111 or outBar terminal 113, to ground. The high output terminal, out terminal 111 or outBar terminal 113, therefore experienced a xe2x80x9cdipxe2x80x9d during the transition when the inputs 151 or 153 switched from high to low and a short circuit current, or crossbar current, path was established from Vdd 102 to ground. This xe2x80x9cdipxe2x80x9d was undesirable and resulted in significant power being wasted.
In addition, the structure of prior art full-rail differential logic circuit 100 was particularly susceptible to noise. This problem was extremely undesirable, and damaging, since, as discussed above, typically, multiple prior art full-rail differential logic circuits 100 were cascaded in long chains (not shown) of prior art full-rail differential logic circuits 100. In these chain configurations, the susceptibility of prior art full-rail differential logic circuit 100 to noise meant that each successive stage of the chain contributed additional noise and was even more adversely affected by the noise than the previous stage. Consequently, a few stages into a chain of prior art full-rail differential logic circuits 100, noise became the dominant factor in the chain.
What is needed is a method and apparatus for creating full-rail differential logic circuits that are capable of efficient use under heavy loads and are therefore more flexible, more space efficient and more reliable than prior art full-rail differential logic circuits. In addition, a full-rail differential logic circuit is needed that does not experience the large xe2x80x9cdipxe2x80x9d experienced by prior art full-rail differential logic circuit 100 and is therefore more power efficient. Finally, it is desirable to have a full-rail differential logic circuit that is more resistant to noise than prior art full-rail differential logic circuit 100.
The clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention include a sense amplifier circuit that is triggered by the delayed clock of the following stage, i.e., the clock input to the sense amplifier circuit of the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention is additionally delayed with respect to the delayed clock that drives the full-rail differential logic. The addition of the sense amplifier circuit, and second delayed clock signal, according to the invention, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the logic network to provide the driver function. Consequently, the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.
In addition, according to the present invention, clocked full-rail differential logic circuits with sense amplifier and shut-off include shut-off devices to minimize the xe2x80x9cdipxe2x80x9d at the high output node that was associated with prior art clocked full-rail differential logic circuits. The shut-off device of the invention isolates the high output terminal immediately from the input terminals when the complementary output terminal is pulled to ground. Consequently, according to the present invention, the window period, or path, for the short circuit current, or crossbar current, is significantly decreased and power is saved.
In addition, since clocked full-rail differential logic circuits with sense amplifier and shut-off include a shut-off device, the high output terminal is isolated from the input terminals and the noise immunity of the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention is significantly better than prior art clocked full-rail differential logic circuits because noise on the input terminal does not affect the high output terminal after evaluation. Consequently, the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention are better suited for application in cascaded chains.
As discussed above, the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention can be cascaded together to form the chains commonly used in the industry. When the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention are cascaded together, the advantages of the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention are particularly evident and the gains in terms of noise immunity, power efficiency, size reduction and flexibility are further pronounced.
In particular, one embodiment of the invention is a cascaded chain of clocked full-rail differential logic circuits with sense amplifier and shut-off. The chain includes a first clocked full-rail differential logic circuit with sense amplifier and shut-off. The first clocked full-rail differential logic circuit with sense amplifier and shut-off includes: a first clocked full-rail differential logic circuit with sense amplifier and shut-off first clock input terminal; at least one first clocked full-rail differential logic circuit with sense amplifier and shut-off data input terminal; at least one first clocked full-rail differential logic circuit with sense amplifier and shut-off data output terminal; and a first clocked full-rail differential logic circuit with sense amplifier and shut-off second clock input terminal.
The cascaded chain of the invention also includes a second clocked full-rail differential logic circuit with sense amplifier and shut-off. The second clocked full-rail differential logic circuit with sense amplifier and shut-off includes: a second clocked full-rail differential logic circuit with sense amplifier and shut-off first clock input terminal; at least one second clocked full-rail differential logic circuit with sense amplifier and shut-off data input terminal; at least one second clocked full-rail differential logic circuit with sense amplifier and shut-off data output terminal; and a second clocked full-rail differential logic circuit with sense amplifier and shut-off second clock input terminal.
According to the invention, the at least one first clocked full-rail differential logic circuit with sense amplifier and shut-off data output terminal is coupled to the at least one second clocked full-rail differential logic circuit with sense amplifier and shut-off data input terminal to form the chain.
According to the invention, a first clock signal is coupled to the first clocked full-rail differential logic circuit with sense amplifier and shut-off first clock input terminal and a second clock signal is coupled to the first clocked full-rail differential logic circuit with sense amplifier and shut-off second clock input terminal and the second clocked full-rail differential logic circuit with sense amplifier and shut-off first clock input terminal. According to the invention, the second clock signal is delayed with respect to the first clock signal by a predetermined delay time.
In one embodiment of the invention, a delay circuit is coupled between the first clocked full-rail differential logic circuit with sense amplifier and shut-off first clock input terminal and the second clocked full-rail differential logic circuit with sense amplifier and shut-off first clock input terminal to provide the predetermined delay time. In one embodiment of the invention, the delay circuit is also coupled between the first clocked full-rail differential logic circuit with sense amplifier and shut-off first clock input terminal and the first clocked full-rail differential logic circuit with sense amplifier and shut-off second clock input terminal to provide the predetermined delay time.
One embodiment of the invention is a clocked full-rail differential logic circuit with sense amplifier and shut-off that includes a clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal and a clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off also includes a first node, the first node is coupled to a first supply voltage.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off also includes a first transistor, the first transistor including a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode. The first node is coupled to the first transistor first flow electrode and the first transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal. The first transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off also includes a second transistor, the second transistor including a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode. The first node is coupled to the second transistor first flow electrode and the second transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off also includes a third transistor, the third transistor including a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode. The first transistor control electrode is coupled to the third transistor first flow electrode and the clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal. The second transistor control electrode is coupled to the third transistor second flow electrode and the clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal. The third transistor control electrode is coupled to a clock signal CLKA.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off also includes a fourth transistor, the fourth transistor including a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode. The first node is coupled to the fourth transistor first flow electrode and the fourth transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal. The fourth transistor control electrode is coupled to the clock signal CLKA. The fourth transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off also includes a fifth transistor, the fifth transistor including a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode. The first node is coupled to the fifth transistor first flow electrode and the fifth transistor second flow electrode is coupled to the clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal. The fifth transistor control electrode is coupled to the clock signal CLKA. The fifth transistor can also include a back bias input terminal having a back bias voltage thereon.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off also includes a sense amplifier circuit coupled between the clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal and the clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit includes a sixth transistor, the sixth transistor including a sixth transistor first flow electrode, a sixth transistor second flow electrode and a sixth transistor control electrode. The first transistor second flow electrode is coupled to the sixth transistor first flow electrode. The sixth transistor second flow electrode is coupled to a second node. The sixth transistor control electrode is coupled to the third transistor first flow electrode and the clocked full-rail differential logic circuit with sense amplifier and shut-off outbar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit also includes a seventh transistor, the seventh transistor including a seventh transistor first flow electrode, a seventh transistor second flow electrode and a seventh transistor control electrode. The second transistor second flow electrode is coupled to the seventh transistor first flow electrode. The seventh transistor second flow electrode is coupled to the second node. The seventh transistor control electrode is coupled to the third transistor second flow electrode and the clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit also includes an eighth transistor, the eighth transistor including an eighth transistor first flow electrode, an eighth transistor second flow electrode and an eighth transistor control electrode. The eighth transistor first flow electrode is coupled to the second node and the eighth transistor second flow electrode is coupled to a second supply voltage. A clock signal CLKB is coupled to the eighth transistor control electrode of the clocked full-rail differential logic circuit with sense amplifier and shut-off sense amplifier circuit. In one embodiment of the invention, the clock signal CLKB is delayed a predetermined time with respect to the clock signal CLKA.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off also includes a shut-off device coupled between the clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal and the clocked full-rail differential logic circuit with sense amplifier and shut-off outBar terminal and the logic network out terminal and logic network outBar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off shut-off device includes a ninth transistor, the ninth transistor including a ninth transistor first flow electrode, a ninth transistor second flow electrode and a ninth transistor control electrode. The fourth transistor second flow electrode is coupled to the ninth transistor first flow electrode. The ninth transistor second flow electrode is coupled to the logic network out terminal. The ninth transistor control electrode is coupled to the third transistor first flow electrode and the clocked full-rail differential logic circuit with sense amplifier and shut-off outbar terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off shut-off device also includes a tenth transistor, the tenth transistor including a tenth transistor first flow electrode, a tenth transistor second flow electrode and a tenth transistor control electrode. The fifth transistor second flow electrode is coupled to the tenth transistor first flow electrode. The tenth transistor second flow electrode is coupled to the logic network outBar terminal. The tenth transistor control electrode is coupled to the third transistor second flow electrode and the clocked full-rail differential logic circuit with sense amplifier and shut-off out terminal.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off also includes a logic network, the logic network including at least one logic network input terminal, a logic network out terminal and a logic network outBar terminal. The logic network out terminal is coupled to the second flow electrode of the ninth transistor and the logic network outBar terminal is coupled to the second flow electrode of the tenth transistor.
In one embodiment of the invention, the clocked full-rail differential logic circuit with sense amplifier and shut-off also includes a eleventh transistor, the eleventh transistor including a eleventh transistor first flow electrode, a eleventh transistor second flow electrode and a eleventh transistor control electrode. The eleventh transistor first flow electrode is coupled to the logic network. The eleventh transistor control electrode is coupled to the clock signal CLKA. The eleventh transistor second flow electrode is coupled to the second supply voltage.
As discussed in more detail below, the clocked full-rail differential logic circuits with sense amplifier and shut-off of the invention are capable of efficient use under heavy loads and are therefore more flexible, more space efficient and more reliable than prior art full-rail differential logic circuits. In addition, the present invention provides a full-rail differential logic circuit with shut-off that does not experience the large xe2x80x9cdipxe2x80x9d experienced by prior art full-rail differential logic circuits and is therefore more power efficient. In addition, the present invention provides a full-rail differential logic circuit with shut-off that is more resistant to noise than prior art full-rail differential logic circuits.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.